In general, CMOS semiconductor devices include integrated circuits having complementary pairs of P-channel field-effect transistors and N-channel field-effect transistors formed on a common semiconductor substrate. As is generally known in the art, CMOS technologies are typically used to fabricate IC (integrated circuit) chips for high density and high-performance applications due to, e.g., the high operation efficiency, high switching speed, and good scaling properties that are characteristic of CMOS devices. Technological innovations in semiconductor fabrication technologies are driving market demands for CMOS solutions for higher speed, higher integration density, and lower power applications. The downscaling of CMOS technologies to submicron design rules and beyond, however, poses technological challenges with respect to maintaining performance and reliability. For example, as device sizes are downscaled, CMOS transistors must be formed with, e.g., thinner gate electrodes, smaller channel lengths, and shallower drain/source extension diffusion regions. This downscaling generally results in transistors having higher channel resistance and higher junction/contact parasitic resistances, leading to degraded performance. To mitigate the impact on device performance with downscaling, various state of the art CMOS fabrication techniques can be implemented to effectively reduce parasitic gate and junction resistances and increase channel conductivity.
For example, DSL (dual stress liner) techniques can be incorporated in CMOS process flows as a means to enhance performance of highly-scaled CMOS devices. In general, DSL technologies are premised on findings that the application of a sufficient compressive stress to the conduction channel of a P-type transistor can improve the carrier (holes) mobility within the channel, while the application of a sufficient tensile stress to the conduction channel of an N-type transistor can improve the carrier (electrons) mobility within the channel. In this regard, various DSL techniques that have been developed to improve device performance by forming a compressive stress insulating liner over the gate structure of P-type transistors while forming tensile stress insulating liners over the gate structures of N-type transistor devices, for the purposes of increasing the charge carrier mobility in the transistor channels.
FIG. 1 is a cross-sectional schematic view of a dual stress liner CMOS device having a conventional framework. FIG. 1 illustrates a CMOS semiconductor device (100) having NMOS and PMOS transistor structures (110) and (120) formed in respective active regions (102) and (103) on an active surface of a semiconductor substrate (101). The active regions (102) and (103) are defined and separated by an isolation structure (104) (e.g., STI (shallow trench isolation) structure). In the illustrative embodiment, the active region (102) is defined by a portion of a P-type substrate layer (101a) and the active region (103) comprises an N-type device well (101b) formed in the P-type substrate layer (101a). The NMOS transistor (110) comprises a gate structure (111) formed on the substrate surface in the active region (102), as well as n-doped drain/source diffusion regions (16) formed in the p-type substrate layer (101a). Similarly, the PMOS transistor (120) comprises a gate structure (121) formed on the substrate surface in the active region (103), as well as p-doped drain/source diffusion regions (16) formed in the N-well (101b). The source/drain regions (16) of the transistors (110) and (120) include metal silicide contact regions (17).
The gate structures (111) and (121) have similar structures, each comprising a polysilicon (poly-Si) gate electrode (11/12/13) formed of stacked layers including a dielectric layer (11), a polysilicon layer (12) and a metal silicide layer (13). Moreover, the gate structures (111) and (121) each have thin L-shaped sidewall insulating spacer layers (14) formed on the sidewalls of the gate electrodes (11/12/13) and a portion of the surface of the active silicon regions adjacent the sidewalls. A polyconductor structure (131) is formed over the isolation region (104), which comprises a polysilicon layer (12′) and metal silicide layer (13′) similar to the gate structures (111) and (121). As is known in the art, the polyconductor structure (131) may be part of an electrical interconnection that is formed simultaneously and integrally with the gate structures (111) and (121), which serves to connect the gate electrodes of the complementary transistor pairs (110) and (120), for example.
Further, different stress-imparting insulating films (140, 160) are formed over the active surface of the semiconductor substrate (101) to form a DSL structure that imparts appropriate stresses to enhance the channel conductivity of the CMOS transistors (110) and (120). The stress films (140) and (160) may be formed using a conventional dual stress liner process flow in which two different nitrides films 140 and 160 are formed using separate lithographic patterning steps. For example, in the embodiment of FIG. 1, a tensile nitride film (140) and thin oxide layer (150) can be sequentially deposited over the active surface of the substrate (101) and then patterned to remove those portions of the films (140) and (150) that cover the PMOS region (103). Thereafter, a compressive nitride film (160) can be deposited over the active surface of the substrate and then patterned to remove that portion of the compressive nitride film (160) that covers the NMOS region (102), wherein the oxide layer (150) as an etch stop layer.
The various DSL structure layers (140), (150) and (160) may be formed in a manner, such as depicted in FIG. 1, such that the compressive stress liner (160) overlaps the tensile nitride liner (140) and oxide layer (150). In particular, FIG. 1 illustrates an embodiment where an overlapped region (105) of the stress liners (140/150/160) is located in the isolation region (104) over the polyconductor structure (131). The overlapped region (105) is formed to ensure that there is no gap between the two liner materials (140) and (160). In the illustrative embodiment of FIG. 1, the stress liner layers (140) and (160) are depicted as having the same thickness t1 (e.g., 600 angstroms) and the layer (150) is depicted as having a thickness, t2 (e.g., 100 angstroms). In this regard, the dual stress liner structure has non-uniform thickness in different regions, wherein the DSL structure has a thickness of t1+t2 in the active region (102), a thickness of t1 in the active region (103) and a thickness 2ti+t2 in the overlapped region (105). The non-uniform thickness of the DSL structure may be problematic with regard to subsequent processing steps.
For example, the non-uniformity in thickness of the DSL structure may cause problems during subsequent BEOL processing when etching contact via holes through the different regions (overlapped and non-overlapped regions) of the DSL structure to form contacts to underlying polysilicon contact regions (13), (13′) and (17). In some conventional techniques, a reactive ion etch (RIE) process is used to concurrently etch openings in the DSL layers to expose the metal silicide regions (13), (13′) and (17) in both the overlapped region (105) and non-overlapped regions of the DSL layers. To accommodate for the non-uniform thickness of the DSL layers, an over-etch RIE process is performed to ensure that a contact opening is sufficiently formed in the overlapped region (105) to expose the underlying metal contact (13′). Such over-etching, however, can cause damage to and/or erosion of the metal silicide regions (13, 17) that are exposed during the via contact etch in the non-overlapped regions of the DSL structure. This conventional process and the associated defect mechanisms will be explained in further detail with reference to FIG. 2.
FIG. 2 schematically illustrates a stage of BEOL fabrication where an ILD (interlayer dielectric) layer (200) is been formed over the active surface of the semiconductor device of FIG. 1, and where a plurality of contact holes (201)˜(204) are formed through the ILD layer (200) to some of the silicide contacts (13) and (17) of the transistors (110) and (120) in non-overlapped regions of the DSL layers (140/150) and (160) and to the silicide contact (13′) in the overlapped region (105) of the DSL layers. In general, the contact holes (201)˜(204) can foe formed by a first etch process to form contact holes in the ILD layer (200) down to the respective stress liners (140) and (160) using an conventional RIE etch process with an etch chemistry that etches the materials of the ILD layer (200) and liner layer (150) (e.g., oxides) selective to stress liner material (e.g., nitride), whereby the stress layers (140, 160) used as etch stops. Thereafter, a second etch process is performed to concurrently etch the portions of the stress liner layers (140/150) and (160) that are aligned with, and exposed through, the respective via holes (201)˜(204) down to the underlying silicide regions (13, 13′ and 17). The second etch process can be performed using an conventional RIE etch process with an etch chemistry that etches the materials of the liner layers (140/150) and (160) selective to of the ILD layer (200), wherein the underlying silicide regions (13, 13′ and 17) are used as etch stops.
Due to the variation in the total thicknesses of the overlapped region (105) and non-overlapped regions of the DSL layers, the second etch process must foe performed for a sufficient amount of time so that the contact hole (204) is appropriately etched through ail stress liner layers (160-150-140) to expose the silicide layer (13′) of the polysilicon conductor (131), otherwise a contact open failure can result. In other words, in the conventional process, the RIE etch is performed based on thicker portion of the DSL in the overlapped region (105) (i.e., the combined thickness of the stress layers (140/150/160)), as compared to the thinner portion of the DSL in the non-overlapped. In this regard, while the second etch process is performed to extend the contact holes through the DSL layers to the silicide contacts (13, 13′ and 17), the contact holes (201), (202) and (203) in the non-overlapped regions of the DSL layers will be etched down to the silicide contacts (135 and (17) before the contact hole (204) in the overlapped region (105) is etched to expose the silicide contact (13′). Consequently, while the etch process is continued to sufficiently etch the contact hole (204) to the silicide layer (13′) in the overlapped region (105), the exposed silicide contacts (13) and (17) in the contact holes (210, 202 and 203) can be damaged from exposure to the etching environment. For instance, FIG. 2 illustrates one possible defect mechanism in which the thin silicide contact layers 13 and 17 at the bottom of the contact holes (201, 202, and 203) are significantly over-etched. In other instances, severe over etching can result in defects such as punch through the silicide contact layers (13) and (17) or unwanted residual material, all of which causing higher resistance contact interfaces between device contacts and the metal plugs subsequently formed in the contact holes during later stages of BEOL fabrication.